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A-LevelComputer ScienceProcessor fundamentals9618/12 · Oct/Nov 2021 · Q815 Marks

The Von Neumann model for a computer system uses registers.

  1. (a)(i)Describe the role of the following special purpose registers in the fetch-execute (F-E) cycle. Memory Address Register (MAR) Memory Data Register (MDR)[4]
  2. (a)(ii)Another special purpose register is the Index Register. Identify one other special purpose register used in the Von Neumann model for a computer system.[1]
  3. (b)(i)In the following table, each row shows the current contents of the ACC in binary and the instruction that will be performed on those contents. Complete the table by writing the new contents of the ACC after the execution of each instruction. Current contents of the ACC Instruction New contents of the ACC 01010101 XOR 101 11110000 AND 104 00001111 LSL #4 11111111 OR 102[4]
  4. (b)(ii)The following table contains five assembly language instruction groups. Write an appropriate assembly language instruction for each instruction group, using the given instruction set. The first one has been completed for you. Instruction Group Instruction Data movement LDM #2 Input and output of data Arithmetic operations Unconditional and conditional instructions Compare instructions[4]
  5. (b)(iii)The opcode LDM uses immediate addressing. The opcode LDD uses direct addressing. Identify and describe one additional mode of addressing. Mode of addressing Description[2]

Mark scheme

Marking points from the official mark scheme (Oct/Nov 2021). The mark or mark type is shown in brackets.

  1. [1] MAR: Stores the next address to be fetched
  2. [1] MAR: ... held in the Program Counter (PC)
  3. [1] MAR: The data at this address is then fetched
  4. [1] MDR: Stores the data from the address pointed to by the MAR
  5. [1] MDR: The data in it is copied to the Current Instruction Register (CIR)
  6. [1] Program Counter (PC) / Current Instruction Register (CIR) / Status register / Interrupt register
  7. [1] 01010101 XOR (memory[101]=11110000) = 10100101
  8. [1] 11110000 AND (memory[104]=11111111) = 11110000
  9. [1] 00001111 LSL #4 = 11110000
  10. [1] 11111111 OR (memory[102]=00001111) = 11111111
  11. [1] Input and output of data: IN / OUT
  12. [1] Arithmetic Operations: INC ACC / INC IX
  13. [1] Unconditional and conditional instructions: JPN 100 / JMP 100
  14. [1] Compare instructions: CMP 100
  15. [1] Mode of addressing: Indirect addressing / Relative addressing / Indexed addressing
  16. [1] Description (for Indirect addressing): the address to be used is at the given address
  17. [1] Description (for Relative addressing): the address to be used is an offset number of locations away, relative to the address of the current instruction
  18. [1] Description (for Indexed addressing): form the address from the given address plus the contents of the index register

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About this question

Topic
Processor fundamentals, A-Level Computer Science (syllabus 9618). Structured question, 15 marks.
Source
A-Level Computer Science, Oct/Nov 2021 Paper 1 Variant 2, question 8.

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