A-LevelComputer ScienceProcessor Architecture and Assembly LanguageMay/June 2024Paper 1 Q57 Marks
The following table shows part of the instruction set for a processor. The processor has two registers: the Accumulator (ACC) and an Index Register (IX). Instruction Opcode Operand Explanation LDM #n Immediate addressing. Load the number n to ACC LDD <address> Direct addressing. Load the contents of the location at the given address to ACC LDI <address> Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC LDX <address> Indexed addressing. Form the address from <address> + the contents of the index register. Copy the contents of this calculated address to ACC LDR #n Immediate addressing. Load the number n to IX ADD #n/Bn/&n Add the number n to the ACC ADD <address> Add the contents of the given address to the ACC SUB #n/Bn/&n Subtract the number n from the ACC SUB <address> Subtract the contents of the given address from the ACC INC <register> Add 1 to the contents of the register (ACC or IX) <address> can be an absolute or a symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001010 & denotes a hexadecimal number, e.g. &4A
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