The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (IX). [Table: Instruction (Opcode, Operand, Explanation)] <address> can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 The following table shows another part of the instruction set for the processor. [Table: Instruction (Opcode, Operand, Explanation)] The contents of memory addresses 50 and 51 are shown: [Table: Memory address, Data value (50: 01001101, 51: 10001111)]

1. (a)Trace the program currently in memory using the trace table, stopping when line 90 is executed for a second time. [Table of program instructions and memory contents for trace table][5]
2. (b)(i)The current contents of the ACC are: 0 1 0 1 0 0 1 1 Show the contents of the ACC after the execution of the following instruction. XOR B00011111[1]
3. (b)(ii)The current contents of the ACC are: 0 1 0 1 0 0 1 1 Show the contents of the ACC after the execution of the following instruction. AND 50[1]
4. (b)(iii)The current contents of the ACC are: 0 1 0 1 0 0 1 1 Show the contents of the ACC after the execution of the following instruction. LSL #3[1]
5. (b)(iv)The current contents of the ACC are: 0 1 0 1 0 0 1 1 Show the contents of the ACC after the execution of the following instruction. OR 51[1]
6. (c)Write the register transfer notation for each of the stages in the fetch-execute cycle described in the table. [Table: Description, Register transfer notation][3]