Describe the use of pipelining in Reduced Instruction Set Computers (RISC).

Mark scheme

Marking points from the official mark scheme (May/June 2023). The mark or mark type is shown in brackets.

1. [2] One mark per mark point (Max 2) MP1 Pipelining allows several instructions to be processed simultaneously / concurrently. MP2 therefore, increasing the CPU instruction throughput / the number of instructions completed per unit of time. MP3 Each instruction stage / subtask is completed during one clock cycle MP4 No two instructions can execute their same stage of instruction / subtask at the same clock cycle. MP5 ... e.g., while one instruction is being decoded, the next instruction can be fetched, etc.
2. [4] One mark per mark point (Max 4) • First stage of first instruction in first clock cycle • First instruction successfully completed over five clock cycles • Remaining instructions completed over ten clock cycles ... • ... with no extra instruction sections added on any row. Example answer 1 Processor stages Clock cycles 1 2 3 4 5 6 7 8 9 10 11 12 IF 1.1 2.1 3.1 4.1 5.1 6.1 ID 1.2 2.2 3.2 4.2 5.2 6.2 OF 1.3 2.3 3.3 4.3 5.3 6.3 IE 1.4 2.4 3.4 4.4 5.4 6.4 WB 1.5 2.5 3.5 4.5 5.5 6.5 Example answer 2 Processor stages Clock cycles 1 2 3 4 5 6 7 8 9 10 11 12 IF A B C D E F ID A B C D E F OF A B C D E F IE A B C D E F WB A B C D E F