O-LevelComputer ScienceHardware2210/11 · May/June 2015 · Q78 Marks

One of the key features of von Neumann computer architecture is the use of buses.

(a)Three buses and three descriptions are shown below. Draw a line to connect each bus to its correct description. [Figure showing three bus names (address bus, control bus, data bus) in a left column and three descriptions in a right column, with space to draw lines.][2]
(b)The seven stages in a von Neumann fetch-execute cycle are shown in the table below. Put each stage in the correct sequence by writing the numbers 1 to 7 in the right hand column. The first one has been done for you. [Table with columns: Stage, Sequence number. Stages listed with one '1' pre-filled in Sequence number column.][6]

This question uses a diagram from the original paper, which isn't shown here. Open the full paper from the past papers archive to see it.

Mark scheme

Marking points from the official mark scheme (May/June 2015). The mark or mark type is shown in brackets.

[(a)] 2/3 matches - 2 marks
[(a)] 1 match - 1 mark
[(a)] Correct connections: address bus -> this uni-directional bus carries signals relating to memory addresses between processor and memory; control bus -> this bus carries signals used to coordinate the computer's activities; data bus -> this bi-directional bus is used to exchange data between processor, memory and input/output devices
[(b)] Sequence for each stage:
[(b)] the PC (program counter) contains the address of the next instruction to be fetched -> 1
[(b)] the address contained in the PC (program counter) is copied to the MAR (memory address register) via the address bus -> 2
[(b)] the instruction is then copied from the memory location contained in the MAR (memory address register) and is placed in the MDR (memory data register) -> 3
[(b)] the entire instruction is then copied from the MDR (memory data register) and placed in the CIR (current instruction register) -> 4
[(b)] the value in the PC (program counter) is then incremented so that it points to the next instruction to be fetched -> 5*
[(b)] the address part of the instruction, if any, is placed in the MAR (memory address register) -> 6
[(b)] the instruction is finally decoded and is then executed -> 7
[(b)] The incrementation of the program counter can appear at any stage after 2. All other stages must be in the correct given order.

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