A computer with a Von Neumann architecture has a central processing unit (CPU) that performs the fetch-decode-execute (FDE) cycle.

Mark scheme

Marking points from the official mark scheme (Oct/Nov 2025). The mark or mark type is shown in brackets.

1. [5] One mark for each correct part of the diagram. The diagram shows: • CIR is built into CU • CIR stores instruction • CU decodes the instruction • Instruction is decoded using an instruction set // Instruction is separated into opcode and operand • Signal is sent from CIR to ALU (to execute) • CU sends signal to RAM to fetch any data needed for instruction • ACC is built into ALU • ACC stores any data needed for instruction • ALU executes the instruction // ALU performs the mathematic/logical operation (needed by the instruction)
2. [2] Any two from: • Independent/self-contained processing unit • It executes/processes instructions // It performs the FDE cycle • It contains registers/units (to process data)
3. [4] Four from (MAX 2 if no expansion given): • The number of cores could be increased // by example ... • ... this means that more instructions can be processed simultaneously • The clock speed could be increased // by example ... • ... this means that more instructions can be processed (by a core) per second • The cache could be increased // by example ... • ... this means that more frequently used data/instructions can be stored (to be accessed faster than RAM)